(a) Technical Field of the Invention
The present invention is generally related to clock generation methods and systems, and more particularly to a method and a system recognizing the relationship between pulse periods so as to produce synchronized clock.
(b) Description of the Prior Art
Data transmission between devices requires that the devices' clocks must be synchronized so that the data can be accurately received and decoded. For example, data transmission over interfaces such as USB (Universal Serial Bus), SATA (Serial Advanced Technology Attachment), or PCIE (Peripheral Component Interconnect Express) must have the clocks synchronized in advance before the transmission is actually conducted. Especially for high-speed data transmission interface such as USB 2.0 or 3.0, achieving accurate and quick clock synchronization is a key issue.
Conventionally, clock synchronization is achieved by techniques such as phase lock loop (PLL) or delay lock loop (DLL). However, these techniques have limitations such as the requirement for an input reference clock, long data training sequence, extended synchronization time, complex frequency locking circuit, etc.
Additionally, some techniques require an external crystal or ceramic oscillator for the generation of clock pulses. Despite that, sometimes synchronization still fails to achieve between the master and slave devices. The crystal or ceramic oscillator would also add to the production cost.